1. Field of the Invention
The invention relates to field programmable gate arrays (FPGAs), and in particular to a structure and method for dynamically adjusting the delay on an FPGA interconnect line.
2. Description of the Background Art
Programmable logic devices (PLDs) are a well known type of digital integrated circuit (IC) that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive and require less time to implement than semi-custom and custom integrated circuits.
One type of PLD, the field programmable gate array (FPGA), typically includes a matrix of configurable logic blocks (CLBs) embedded in a configurable interconnect structure. This collection of configurable logic may be customized by loading configuration data into internal configuration memory cells that define the logic functions of the individual CLBs and the signal paths through the interconnect structure. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA from an external device. The collective states of the individual memory cells then determine the logic function of the FPGA. For a detailed description of one type of FPGA interconnect structure, see Kerry M. Pierce, et al., "Interconnect Architecture For a Field Programmable Gate Array Using Variable Length Conductors," U.S. Pat. No. 5,581,199, issued Dec. 3, 1996, which is incorporated herein by reference.
FIG. 1A is a simplified schematic diagram of a portion of a typical interconnect structure 100. An input terminal 105, typically from a CLB, connects to a horizontal interconnect line 110 via a buffer 120. Horizontal interconnect line 110 is broken into segments 110A-110C via a pair of programmable pass transistors 115A and 115B. A number of identical programmable buffers 125A-125H electrically isolate horizontal interconnect line 110 from vertical interconnect lines 130A-130H. (The terms "horizontal" and "vertical" are used herein for ease of illustration, and do not necessarily describe the precise physical layout of interconnect structure 100.)
A set of memory cells 140A-140C controls the states of the corresponding transistors 135A-135C. Vertical interconnect line 130A can be selectively connected to one or more destination lines 132A-132C by programming the corresponding one of memory cells 140A-140C to turn on respective transistors 135A-135C. Vertical interconnect lines 130B-130H typically include similar transistors; however, those transistors are not shown in FIG. 1A, for ease of illustration.
A specific FPGA interconnect configuration is implemented by defining selected paths through the interconnect structure (e.g., by programming selected ones of programmable pass transistors 115A and 115B, programmable buffers 125A-125H, and memory cells 140A-140C). For example, if a specified logic configuration requires that input terminal 105 be connected to destination line 132A, memory cell 140A is programmed to store a logic one, thereby turning on transistor 135A.
Interconnect line 110 is shown as including two pass transistors 115A and 115B; however, an FPGA interconnect line may include a great many more than two pass transistors. The collective resistances of these series-connected pass transistors can introduce a significant cumulative resistance. Additionally, each interconnect line, buffer, and pass transistor introduces a parasitic capacitance that combines with the inherent resistances of interconnect structure 100 to produce signal propagation delays.
FIG. 1B is an expanded view of the contents of block 145 of FIG. 1A. The parasitic capacitances of various capacitive elements are illustrated using dashed lines to distinguish them from discrete components. Block 145 is shown rotated 90 degrees counter-clockwise with respect to FIG. 1A, for ease of illustration.
Buffer 125A is shown as a conventional CMOS buffer in FIG. 1B, although it may be programmable. Buffer 125A isolates interconnect line segment 110A from the load associated with interconnect line 130A. However, this isolation is not perfect, as a parasitic capacitance 150 capacitively couples the input and output terminals of buffer 125A. Other important parasitic capacitances include capacitors to ground, such as a capacitance 155 associated with interconnect line 130A and capacitances 160A-160C associated with respective destination lines 132A-132C.
When all of transistors 135A-135C are off, capacitances 160A-160C are effectively electrically isolated from interconnect line 110A. The capacitive load on interconnect line 110A is therefore proportional to the series capacitance of capacitances 150 and 155, the value of which is somewhat less than the value of the smaller of capacitances 150 and 155. The combined loading of capacitances 150 and 155 increases the signal propagation delay of interconnect line 110 by some small amount, perhaps on the order of picoseconds.
Turning on transistor 135A connects capacitance 160A in parallel with capacitance 155. Parallel capacitances are additive, so turning on transistor 135A increases the capacitive load on interconnect line 130A to a value proportional to the sum of capacitances 155 and 160A. Thus, with transistor 135A turned on, the capacitive load on interconnect line 110A becomes proportional to the series capacitance of capacitance 150 and the combined capacitances 155 and 160A. This increased capacitive loading imposes a longer delay in interconnect line 110A than would be evident were transistor 135A turned off. Similarly, turning on additional transistors (e.g., 135B and 135C) further increases the capacitive load, and therefore the delay, of interconnect line 110.
The signal paths chosen through interconnect structure 100 are conventionally governed by algorithms implemented in software routines. An FPGA user may exercise some control over the signal paths chosen by the software, but it is not practical for the user to control a significant number of signal paths in a given circuit design. Therefore, the software is left to choose among a large number of different interconnect line and destination line combinations to realize a particular signal path. Unfortunately, this diversity of interconnection combinations means that the delay between two nodes on an FPGA may vary significantly, depending upon the routing choices made by the software. Thus, the myriad possible paths that advantageously make interconnect structure 100 flexible can disadvantageously lead to unpredictable signal propagation delays. There is therefore a need for an interconnect structure in which signal propagation delays can be adjusted for optimum performance.
FPGA performance might also be improved for handling serial data communications. Various modulation schemes have been devised to encode data into a serial format, allowing that data to be conveyed over a single electrical or optical conductor. Such schemes are conventionally self-clocking, which is to say that the clock used to interpret the input signal is derived from the input signal itself. Unfortunately, many random and systematic perturbations typically corrupt the signal. These perturbations can cause the timing relationship between the derived clock and the data signal to vary, causing noise conditions commonly referred to as "drift" and "jitter." These conditions differ in that drift occurs over a time period that is long relative to the period of the derived clock, whereas jitter occurs over a time period that is short relative to the period of the derived clock. Hamre provides a more detailed discussion of jitter, including conventional methods for measuring jitter, in U.S. Pat. No. 5,481,563, which is incorporated herein by reference.
FPGAs can be particularly sensitive to jitter and drift due to the potential for unpredictable delay periods associated with the interconnect structure. There is therefore a need for a mechanism for testing an FPGA for jitter and/or drift sensitivity, and for adjusting signal propagation delays where necessary to eliminate such sensitivity.